Recently, the use of silicon-oxide-nitride-oxide-silicon (SONOS) memory devices has increased. SONOS memory devices typically have a charge trapping layer between the dielectric films instead of a floating gate like conventional stack gate memory devices. The SONOS memory devices may also include metal-oxide-nitride-oxide-silicon (MONOS) devices.
Programmable read only memory (PROM) devices having charge trapping layers are discussed, for example, in U.S. Pat. No. 5,768,192 to Boaz Eitan, entitled NON-VOLATILE SEMICONDUCTOR MEMORY CELL UTILIZING ASYMMETRICAL CHARGE TRAPPING. As discussed therein, 2 bits of data may be stored in each memory cell. FIG. 1 is a cross section illustrating a SONOS memory cell capable of storing 2 bits of data per memory cell as discussed in U.S. Pat. No. 5,768,192.
As illustrated in FIG. 1, the 2-bit SONOS memory cell includes an integrated circuit substrate 110, source and drain regions 112 and 114, respectively, a first dielectric layer 120, a charge trapping layer 130, a second dielectric layer 140 and a gate contact 180. The first dielectric layer 120 is provided on the substrate 110, the charge trapping layer 130 is provided on the first dielectric layer 120, the second dielectric layer 140 is provided on the charge trapping layer 130 and the gate contact 180 is provided on the second dielectric layer 140. The charge trapping layer 130 typically includes silicon nitride, which has excellent charge trapping characteristics. Charges may be stored at charge trapping sites 132, which are located at both ends of the charge trapping layer 130. Although silicon nitride has excellent charge trapping characteristics, it cannot typically completely prevent migration of the trapped charges between the charge trapping sites 132. If migration of charges occurs, threshold voltages of the device may vary, which may decrease the reliability of the device.
As semiconductor devices become more integrated, the likelihood of the occurrence of the short channel effects may increase. In these devices, a width of the charge trapping layer 130 may also decrease, decreasing the gap between the charge trapping sites 132. A narrow gap between the charge trapping sites 132, may increase the likelihood of migration. Even a slight migration of the trapped charges can deteriorate the reliability of the deviceso that it may be difficult to store 2 data bits in a single memory cell.
Devices having a pair of trapping patterns 230a, as illustrated in FIG. 2, have been developed to address issues caused by the decreasing size of semiconductor devices. As illustrated in FIG. 2, the memory cell includes an integrated circuit substrate 210, a source region 212, a drain region 214, a first dielectric layer 220, a pair of charge trapping patterns 230a, a pair of dielectric patterns 240a and a gate contact 280. The first dielectric layer 220 has a width similar to a width of the gate contact 280. The pair of charge trapping patterns 230a are separated from each other in order to reduce the likelihood if the migration of the trapped charges. Although the structure of FIG. 2 may address problems of migration, it may not address the problems experiences as a result of the short channel effect.